Research
Embedding intelligence into the silicon design flow.
Chip design at advanced nodes is a search over an astronomically large space, run under tight PPA budgets and slow signoff loops. We build models that learn design structure and validate them where it counts: in the full flow, at signoff.
Standard-Cell Design & DTCO
Design-technology co-optimization (DTCO) at the cell level. We synthesize area-optimal standard cells for complementary FET (CFET) technology through optimal transistor folding and placement, design multi-skewed multi-bit flip-flop (MBFF) cells for useful-skew timing optimization, and boost pin accessibility through cell layout diversification and replacement.
MBFF & Useful Skew
Pin Accessibility
ML-driven Physical Design
Prediction models that make physical design converge faster. We predict design rule check (DRC) hotspots from placement, resolve design rule violations (DRVs) with gradient-based placement refinement that stays legalizable, optimize placement for pin accessibility, and extract interconnect capacitance with learned models.
DRV Resolution
DRC Hotspot Prediction
Pin Accessibility
Capacitance Extraction
AI for Analog Circuit Design
Learning-based analog design automation. We optimize transistor sizing with model-based reinforcement learning (RL) and landscape-aware search guided by topological data analysis (TDA), and learn analog circuit representations with domain-aware hypergraph transformers.
Transistor Sizing
Representation Learning
Advanced Technology
Design methodologies for emerging technologies. We build design enablement for complementary FET (CFET) and physical design flows for monolithic 3D integrated circuits, including 3D via allocation tightly linked with routing optimization.
Monolithic 3D