Research

The AIDA Lab investigates next-generation methods for automating and optimizing electronic design. Our work combines machine learning, optimization theory, and circuit design principles to address challenges in design productivity, quality, and scalability for advanced semiconductor processes.

AI-aided Design Automation

We develop intelligent algorithms that learn from historical design data to guide decision-making across digital and analog design flows. By combining graph neural networks, transformers, and reinforcement learning with classical EDA heuristics, our approaches achieve faster convergence to optimized solutions with fewer costly simulation iterations.

GNN · Transformer · RL · EDA
DTCO · Cell Gen.

Design Technology Co-Optimization (DTCO)

DTCO is essential for pushing the density and performance limits of modern semiconductors. We co-optimize standard cell architectures, power/signal routing strategies, and physical constraints with technology-specific rules. Our work includes AI-driven standard cell layout generation and metal-fill-aware library optimization.

DTCO · Std. Cell · Physical Design
nFET / pFET · CFET

Advanced Node Design Methodology

As technology scales below 3 nm, new device architectures — GAA nanosheets, CFET (complementary FET) — demand entirely new design methodologies. We develop process design kits (PDK), LVS/DRC/RCX rule frameworks, and TCAD-to-SPICE extraction flows for these emerging technologies.

GAA · CFET · PDK · 3 nm
Agent Reward State

Reinforcement Learning for Circuit Optimization

We build RL-based optimization pipelines that iteratively improve circuit topologies and sizing by exploring a design space with learned reward functions. Applications include parasitic-aware SPICE optimization, standard cell PPA improvement, and AutoCkt-style analog circuit sizing.

RL · AutoCkt · SPICE · Analog
Neural Operator · PEX

Neural Operators for Parasitic Extraction

Accurate parasitic extraction (PEX) is critical yet computationally expensive. We train neural operator models (GNO, FNO, DeepONet) on GDS geometry–capacitance dataset pairs to predict coupling capacitances in a fraction of the time of traditional field solvers, enabling fast sign-off quality extraction.

PEX · Neural Operators · GDS · ML
Cell Layout · GDS

AI-driven Standard Cell Library Generation

We leverage GNN and PPO-based reinforcement learning to automate the generation of power-performance-area optimized standard cell layouts. Our approach targets metal-fill-aware placement for sub-3nm libraries and integrates with Calibre DRC/LVS sign-off flows.

GNN · PPO · Std. Cell Library