AIDA Lab · AI-aided Design Automation · Kyung Hee University
We build the tools that design the chips.
AIDA Lab (AI-aided Design Automation) at Kyung Hee University develops machine-learning-driven EDA methodologies, from standard-cell synthesis to physical design and circuit optimization, for advanced technologies.
CMOS standard-cell row: INV · NAND2 · NOR2, transistor-level connectivity as drawn
News
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PaperLegalization-Aware Projected Gradient Descent for DRV Resolution at Placement accepted to MLCAD 2026 as a regular paper.
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PaperATLAS: Adaptive TDA-guided Landscape-Aware Transistor Sizing accepted to ICCAD 2026.
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TalkIEIE 2026 SoC Conference: “Whitening the Black-box: Domain-aware AI for High-Quality Semiconductor Design.”
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PaperHyperAnalog: Domain-Aware Hypergraph Transformer for Analog Circuit Representation Learning accepted to DAC 2026.
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PaperCFET-FP: Complementary FET Standard Cell Synthesis with Optimal Transistor Folding and Placement accepted to TCAD.
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PaperTwo papers accepted to ICCAD 2025: M3: Mamba-assisted Multi-Circuit Optimization via Model-based RL with Effective Scheduling and Capacitance Extraction via Machine Learning with Application to Interconnect Geometry Exploration.
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LabAIDA Lab opens at the Department of Semiconductor Engineering, Kyung Hee University.
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TalkKorean Conference on Semiconductors (KCS): “Standard cells, simple yet powerful design enablements.”
Research
Embedding intelligence into the silicon design flow.
Chip design at advanced nodes is a search over an astronomically large space, run under tight PPA budgets and slow signoff loops. We build models that learn design structure and validate them where it counts: in the full flow, at signoff.
- Standard-Cell Design & DTCO: CFET std. cell, MBFF & useful skew, pin accessibility.
- ML-driven Physical Design: DRV resolution, DRC hotspot prediction, pin accessibility, capacitance extraction.
- AI for Analog Circuit Design: transistor sizing, representation learning.
- Advanced Technology: CFET std. cell, monolithic 3D.
Lab
